1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device that includes a plurality of data holding circuits (flip-flop circuits/latch circuits and the like) for holding data.
2. Description of Related Art
In association with a finer structure and a lower voltage, a software error of a logic circuit, namely, a logic inversion of a data holding circuit and an erroneous data transfer at a time of a signal transmission (Single Event Transient) has become problematic. So, a countermeasure is carried out by connecting a coincidence circuit or a majority logic circuit to the outputs of a plurality of data holding circuits.
However, there is a case that SEU (Single Event Upset/SET (Single Event Transient) of the coincidence circuit itself or the majority logic circuit itself becomes problematic. Therefore, it is important to protect the plurality of data holding circuits from being logically inverted at the same time.
As the related art of the present invention, a technique for improving the SEU resistances of the data holding circuit and the majority logic circuit is disclosed in, for example, “A Digital CMOS Design Technique for SEU Hardening”, written by Mark P. Baze, Steven P. Buchner and Dale McMorrow, IEEE Transactions on Nuclear Science, Vol. 47, No. 6, pp. 2603˜2608, 2000 (non-patent literature 1). In the non-patent literature 1, a transistor is added to the data holding circuit so that the logic inversion is unlikely to occur. FIG. 11 and FIG. 10 in the non-patent literature 1 show countermeasure examples for the data holding circuit (latch circuit) and the majority logic circuit, respectively.
Also, as a method of protecting carriers, which are directly or indirectly generated by radioactive rays, from being collected into a node diffusion layer, an idea for providing a dummy well between a memory cell and a memory cell is proposed in Japanese Patent Publication No. JP-P 2002-353413A (patent literature 1), especially in FIG. 4 in the patent literature 1. The preparation of the foregoing dummy well protects two cells from being inverted at the same time.
The inventor has now discovered the following facts. In the non-patent document 1, the transistor is added to the data holding circuit so that the logic inversion is unlikely to occur. However, there is a problem that a layout area is increased, and there is another problem that the number of the designing steps is increased in order to satisfy specifications (timing) in some cases depending on a circuit configuration.
The fact that the data holding circuits are logically inverted at the same time is exactly equal to the fact that two bits of the memory cells are inverted at the same time. The area of the node diffusion layer in the transistor that configures the data holding circuit in a recent product whose power source voltage is about 1V is similar to the area of the node diffusion layer of the SRAM in the generation of a little while ago. Thus, there is a possibility that the data holding circuits are logically inverted at the same time. The patent literature 1 describes the technique that protects the carriers from being injected into the node diffusion layer in the memory cell, by providing the dummy well between the memory cell and the memory cell. However, there is no countermeasure against a case that a neutron is incident on a Si substrate so that a nuclear reaction causes two or more kinds of ions to be generated at the same time.